1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having a predecoder that decodes an internal address signal to generate an address predecode signal.
2. Description of the Background Art
[Related Art 1]
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), spare rows and columns are provided beforehand in a memory cell array to repair a defect by replacing a defective memory cell that does not operate properly with a spare memory cell in the unit of a row or column. Defective address information must be programmed at the program circuit in the DRAM in order to switch the address to that of a spare memory cell when an address corresponding to the memory cell that does not operate properly (referred to as "defective address" hereinafter) is input in this system. Such a program circuit is generally provided corresponding to each defective address. The method of blowing out a fuse with a laser beam is widely used in the recent memories of a large capacity as the method of programming a defective address.
FIG. 14 is a layout of an example structure of such a program circuit. Referring to FIG. 14, a program circuit P11 is provided corresponding to a defective address FA11, and a program circuit P12 is provided corresponding to a defective address FA12.
Program circuit P11 includes a determination node JN, fuses F10-F13, and N channel MOS transistors QN10-QN13. N channel MOS transistors QN10-QN13 are aligned adjacent to each other. N channel MOS transistors QN10-QN13 have each gate gt connected to corresponding address predecode signal lines X0-X3 by corresponding supply lines DL10-DL13, respectively.
Program circuit P12 includes a determination node JN2, fuses F20-F23, and N channel MOS transistors QN20-QN23 aligned adjacent to each other. N channel MOS transistors QN20-QN23 have each gate gt connected to corresponding address predecode signal lines X0-X3 by corresponding supply lines DL20-DL23, respectively.
In general, the respective program circuits corresponding to a defective address (here, program circuits P11 and P12) are arranged in a centralized manner. More specifically, N channel MOS transistors QN10-QN13 are arranged in a row adjacent to each other in program circuit P11, and N channel MOS transistors QN20-QN23 are arranged in a row adjacent to each other in program circuit P12. Furthermore, N channel MOS transistors QN10-QN13 and QN20-QN23 are arranged in one row as a whole.
The operation of program circuits P11 and P12 will be described hereinafter. The fuse corresponding to the signal at an H level (logical high) of each of bit signals X0-X3 of the address predecode signal corresponding to the defective address is blowed out with a laser beam in advance. Here, it is assumed that address predecode signals X0-X3 corresponding to defective address FA11 is (X0, X1, X2. X3)=(1000), and address predecode signals X0-X3 corresponding to defective address FA12 is (X0, X1, X2. X3)=(0001). In this case, fuses F10 and F23 are blowed out. Determination nodes JN1 and JN2 are precharged to the power supply voltage.
Under this state, address predecode signals X0-X3 are applied to gates gt of N channel MOS transistor QN10-QN13 and QN20-QN23.
When input address predecode signals X0-X3 do not match any of the preprogrammed defective addresses FA11 and FA12, determination nodes JN1 and JN2 are discharged to the level of ground voltage Vss since at least one of N channel MOS transistors QN11-QN13 and QN20-QN22 corresponding to any of fuses F11-F13 and F20-F22 out of fuses F10-F13 and F20-F23 in program circuits P11 and P12 that are not blowed out is turned on. Therefore, redundancy activation signals FUSE1 and FUSE2 of an L level (logical low) are supplied to corresponding spare row decoders to render the spare row decoders inactive.
Next, the case where input address predecode signals X0-X3 match preprogrammed defective address FA11 will be described hereinafter.
In this case, only N channel MOS transistor QN10 corresponding to fuse F10 that is blowed out is turned on in program circuit P11. Therefore, the voltage at determination node JN1 is maintained at the level of the power supply voltage. Redundancy activation signal FUSE1 of an H level is supplied to the corresponding spare row decoder to render the same active. As a result, the defective portion in the memory cell array corresponding to defective address FA11 is repaired.
In program circuit P12, N channel MOS transistor QN20 corresponding to fuse F20 that is not blowed out is turned on, whereby determination node JN2 is discharged to the level of the ground voltage Vss. As a result, redundancy activation signal FUSE2 of an L level is supplied to the corresponding spare row decoder to render the same inactive.
The defective portion of the memory cell array corresponding to defective address FA12 is replaced in a similar manner when input address predecode signals X0-X3 match defective address FA12.
Thus, determination is made whether input address predecode signals X0-X3 match preprogrammed defective addresses FA11 and FA12 to supply redundancy activation signals FUSE1 and FUSE2 of an H level in response to a matching result to render the redundancy circuit active.
[Related Art 2]
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), a predecoder circuit is provided generating an address predecode signal by decoding by every 2 bits or 3 bits an internal address signal generated at an address buffer before being applied to the decoder circuit. The predecoder circuit is provided from the standpoint of reducing the number of transistors forming the decoder circuit, reducing the pitch of pattern layout of the decoder circuit, and increasing the operation speed.
An address predecode signal is applied to the gate of many transistors included in the row decoder circuit and the program circuit . In many cases, the address predecode signal line extends over a long length on the chip. Therefore, the load of the address predecode signal line becomes greater. However, an address predecode signal has a low drivability. Therefore, the delay time of an address predecode signal will become greater.
In view of the foregoing, a repeater circuit is inserted for all the address predecode signal lines from the predecoder. The repeater circuit is formed mainly of an even number of stages of inverter circuits to improve the drivability of the next stage of transistor.
[Problem in Related Art 1]
In accordance with the higher complexity of memory cells, the bit width of the address signal and the address predecode signal is increased. This means that the number of N channel MOS transistors and fuses provided corresponding to the bit signal of the address predecode signal in each program circuit becomes greater.
Also, the number of spare rows and columns provided in the memory cell array is increased. Therefore, the number of program circuits is increased.
Thus, the load on the address predecode signal line becomes greater.
[Problem in Related Art 2]
When the length of an address predecode signal line is great, the insertion of a repeater circuit allows the drivability of the transistor included in the next stage of row decoder circuit and program circuit to be increased to speed the operation.
However, when the length of the address predecode signal line is short or when the load of the address predecode signal line is small, the load of the repeater circuit itself will increase the load of the address predecode signal line to delay the propagation of an address predecode signal.